The present invention in general relates to a data burst transfer between two memory chips on a board or a data burst transfer between two memory circuits on a chip. More particularly, this invention relates to a data burst transfer circuit for carrying out a high-speed data transfer without synchronizing data with a clock signal, and a parallel-serial conversion circuit, a serial-parallel conversion circuit, and an oscillation circuit that can be used for the data burst transfer circuit.
Conventionally, a data transfer has been carried out between memory chips or between memory circuits in synchronism with a clock signal. Therefore, when a clock frequency is slow, the transfer of all data becomes very slow. In order to transfer all data at a high speed when the clock frequency is slow, it is necessary to extremely increase the number of lines for connecting between the memories.
However, the increasing the number of lines for connecting between the memories leads to an increase in the size of a wiring area, which is not preferable. Therefore, when the clock frequency is slow, there may be considered a method of transferring data in synchronism with a high-speed clock signal by generating this high-speed clock using a PLL. However, the provision of the PLL has a problem of making complex the circuit, although it is not necessary to increase the number of lines in this case.
It is an object of the present invention to provide a data burst transfer circuit capable of decreasing the number of lines for connecting between memory chips or between memory circuits and also capable of transferring data at a higher speed, and to provide a parallel-serial conversion circuit, a serial-parallel conversion circuit, and an oscillation circuit that can be used for this data burst transfer circuit.
According to one aspect of the present invention, timing signals (strobe signals) having a plurality of phases are generated based on a signal of a higher frequency than that of a clock signal. A memory at a data transfer origin converts data to be transferred from a parallel signal into a serial signal for each plurality of bits based on the generated strobe signals. This memory then transmits the serial signals to a memory at a data transfer destination via separate signal lines. The memory at the data transfer destination converts the received serial signals into parallel signals based on the strobe signals, thereby returning the data to the original data, and stores this data.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.